[324] | 1 | /* The copyright in this software is being made available under the BSD |
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| 2 | * License, included below. This software may be subject to other third party |
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| 3 | * and contributor rights, including patent rights, and no such rights are |
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| 4 | * granted under this license. |
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| 5 | * |
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| 6 | * Copyright (c) 2010-2013, ITU/ISO/IEC |
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| 7 | * All rights reserved. |
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| 8 | * |
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| 9 | * Redistribution and use in source and binary forms, with or without |
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| 10 | * modification, are permitted provided that the following conditions are met: |
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| 11 | * |
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| 12 | * * Redistributions of source code must retain the above copyright notice, |
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| 13 | * this list of conditions and the following disclaimer. |
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| 14 | * * Redistributions in binary form must reproduce the above copyright notice, |
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| 15 | * this list of conditions and the following disclaimer in the documentation |
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| 16 | * and/or other materials provided with the distribution. |
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| 17 | * * Neither the name of the ITU/ISO/IEC nor the names of its contributors may |
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| 18 | * be used to endorse or promote products derived from this software without |
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| 19 | * specific prior written permission. |
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| 20 | * |
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| 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS |
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| 25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
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| 31 | * THE POSSIBILITY OF SUCH DAMAGE. |
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| 32 | */ |
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| 33 | |
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| 34 | /** \file ContextTables.h |
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| 35 | \brief Defines constants and tables for SBAC |
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| 36 | \todo number of context models is not matched to actual use, should be fixed |
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| 37 | */ |
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| 38 | |
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| 39 | #ifndef __CONTEXTTABLES__ |
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| 40 | #define __CONTEXTTABLES__ |
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| 41 | |
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| 42 | //! \ingroup TLibCommon |
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| 43 | //! \{ |
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| 44 | #define FIX827 1 ///< Fix for issue #827: CABAC init tables |
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| 45 | #define FIX712 1 ///< Fix for issue #712: CABAC init tables |
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| 46 | |
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| 47 | // ==================================================================================================================== |
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| 48 | // Constants |
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| 49 | // ==================================================================================================================== |
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| 50 | |
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| 51 | #define MAX_NUM_CTX_MOD 512 ///< maximum number of supported contexts |
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| 52 | |
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| 53 | #define NUM_SPLIT_FLAG_CTX 3 ///< number of context models for split flag |
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| 54 | #define NUM_SKIP_FLAG_CTX 3 ///< number of context models for skip flag |
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| 55 | |
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| 56 | #define NUM_MERGE_FLAG_EXT_CTX 1 ///< number of context models for merge flag of merge extended |
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| 57 | #define NUM_MERGE_IDX_EXT_CTX 1 ///< number of context models for merge index of merge extended |
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| 58 | |
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| 59 | #define NUM_PART_SIZE_CTX 4 ///< number of context models for partition size |
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| 60 | #define NUM_CU_AMP_CTX 1 ///< number of context models for partition size (AMP) |
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| 61 | #define NUM_PRED_MODE_CTX 1 ///< number of context models for prediction mode |
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| 62 | |
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| 63 | #define NUM_ADI_CTX 1 ///< number of context models for intra prediction |
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| 64 | |
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| 65 | #define NUM_CHROMA_PRED_CTX 2 ///< number of context models for intra prediction (chroma) |
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| 66 | #define NUM_INTER_DIR_CTX 5 ///< number of context models for inter prediction direction |
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| 67 | #define NUM_MV_RES_CTX 2 ///< number of context models for motion vector difference |
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| 68 | |
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| 69 | #define NUM_REF_NO_CTX 2 ///< number of context models for reference index |
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| 70 | #define NUM_TRANS_SUBDIV_FLAG_CTX 3 ///< number of context models for transform subdivision flags |
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| 71 | #define NUM_QT_CBF_CTX 5 ///< number of context models for QT CBF |
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| 72 | #define NUM_QT_ROOT_CBF_CTX 1 ///< number of context models for QT ROOT CBF |
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| 73 | #define NUM_DELTA_QP_CTX 3 ///< number of context models for dQP |
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| 74 | |
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| 75 | #define NUM_SIG_CG_FLAG_CTX 2 ///< number of context models for MULTI_LEVEL_SIGNIFICANCE |
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| 76 | |
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| 77 | #define NUM_SIG_FLAG_CTX 42 ///< number of context models for sig flag |
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| 78 | #define NUM_SIG_FLAG_CTX_LUMA 27 ///< number of context models for luma sig flag |
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| 79 | #define NUM_SIG_FLAG_CTX_CHROMA 15 ///< number of context models for chroma sig flag |
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| 80 | |
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| 81 | #define NUM_CTX_LAST_FLAG_XY 15 ///< number of context models for last coefficient position |
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| 82 | |
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| 83 | #define NUM_ONE_FLAG_CTX 24 ///< number of context models for greater than 1 flag |
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| 84 | #define NUM_ONE_FLAG_CTX_LUMA 16 ///< number of context models for greater than 1 flag of luma |
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| 85 | #define NUM_ONE_FLAG_CTX_CHROMA 8 ///< number of context models for greater than 1 flag of chroma |
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| 86 | #define NUM_ABS_FLAG_CTX 6 ///< number of context models for greater than 2 flag |
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| 87 | #define NUM_ABS_FLAG_CTX_LUMA 4 ///< number of context models for greater than 2 flag of luma |
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| 88 | #define NUM_ABS_FLAG_CTX_CHROMA 2 ///< number of context models for greater than 2 flag of chroma |
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| 89 | |
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| 90 | #define NUM_MVP_IDX_CTX 2 ///< number of context models for MVP index |
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| 91 | |
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| 92 | #define NUM_SAO_MERGE_FLAG_CTX 1 ///< number of context models for SAO merge flags |
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| 93 | #define NUM_SAO_TYPE_IDX_CTX 1 ///< number of context models for SAO type index |
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| 94 | |
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| 95 | #define NUM_TRANSFORMSKIP_FLAG_CTX 1 ///< number of context models for transform skipping |
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| 96 | #define NUM_CU_TRANSQUANT_BYPASS_FLAG_CTX 1 |
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[504] | 97 | |
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| 98 | #if H_3D_ARP |
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| 99 | #define NUM_ARPW_CTX 4 ///< number of context models for weighting factor index used by advanced residual prediction |
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| 100 | #endif |
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| 101 | |
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| 102 | #if H_3D_IC |
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| 103 | #define NUM_IC_FLAG_CTX 3 ///< number of context models for illumination compensation flag |
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| 104 | #endif |
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| 105 | |
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[324] | 106 | #define CNU 154 ///< dummy initialization value for unused context models 'Context model Not Used' |
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| 107 | |
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[531] | 108 | #if H_3D_DIM |
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| 109 | #define NUM_DEPTH_INTRA_MODE_CTX 8 ///< number of context models for depth intra modes |
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| 110 | #define NUM_DDC_FLAG_CTX 2 ///< number of context models for deltaDC flag (DMM or RBC) |
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| 111 | #define NUM_DDC_DATA_CTX 2 ///< number of context models for deltaDC data (DMM or RBC) |
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| 112 | #if H_3D_DIM_DMM |
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| 113 | #define NUM_DMM1_DATA_CTX 1 ///< number of context models for DMM1 data |
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[554] | 114 | #if !SEC_DMM2_E0146 |
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[531] | 115 | #define NUM_DMM2_DATA_CTX 1 ///< number of context models for DMM2 data |
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[554] | 116 | #endif |
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[531] | 117 | #define NUM_DMM3_DATA_CTX 1 ///< number of context models for DMM3 data |
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| 118 | #endif |
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| 119 | #if H_3D_DIM_RBC |
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| 120 | #define NUM_RBC_DATA_CTX 1 ///< number of context models for RBC data |
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| 121 | #endif |
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| 122 | #endif |
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| 123 | |
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| 124 | #if H_3D_DIM_SDC |
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| 125 | #define SDC_NUM_RESIDUAL_FLAG_CTX 1 |
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| 126 | #define SDC_NUM_RESIDUAL_CTX 1 |
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| 127 | #endif |
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[324] | 128 | // ==================================================================================================================== |
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| 129 | // Tables |
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| 130 | // ==================================================================================================================== |
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| 131 | |
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| 132 | // initial probability for cu_transquant_bypass flag |
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| 133 | static const UChar |
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| 134 | INIT_CU_TRANSQUANT_BYPASS_FLAG[3][NUM_CU_TRANSQUANT_BYPASS_FLAG_CTX] = |
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| 135 | { |
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| 136 | { 154 }, |
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| 137 | { 154 }, |
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| 138 | { 154 }, |
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| 139 | }; |
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| 140 | |
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| 141 | // initial probability for split flag |
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| 142 | static const UChar |
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| 143 | INIT_SPLIT_FLAG[3][NUM_SPLIT_FLAG_CTX] = |
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| 144 | { |
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| 145 | { 107, 139, 126, }, |
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| 146 | { 107, 139, 126, }, |
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| 147 | { 139, 141, 157, }, |
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| 148 | }; |
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| 149 | |
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| 150 | static const UChar |
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| 151 | INIT_SKIP_FLAG[3][NUM_SKIP_FLAG_CTX] = |
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| 152 | { |
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| 153 | { 197, 185, 201, }, |
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| 154 | { 197, 185, 201, }, |
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| 155 | { CNU, CNU, CNU, }, |
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| 156 | }; |
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| 157 | |
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| 158 | static const UChar |
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| 159 | INIT_MERGE_FLAG_EXT[3][NUM_MERGE_FLAG_EXT_CTX] = |
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| 160 | { |
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| 161 | { 154, }, |
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| 162 | { 110, }, |
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| 163 | { CNU, }, |
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| 164 | }; |
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| 165 | |
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| 166 | static const UChar |
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| 167 | INIT_MERGE_IDX_EXT[3][NUM_MERGE_IDX_EXT_CTX] = |
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| 168 | { |
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| 169 | { 137, }, |
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| 170 | { 122, }, |
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| 171 | { CNU, }, |
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| 172 | }; |
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| 173 | |
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| 174 | static const UChar |
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| 175 | INIT_PART_SIZE[3][NUM_PART_SIZE_CTX] = |
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| 176 | { |
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| 177 | { 154, 139, CNU, CNU, }, |
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| 178 | { 154, 139, CNU, CNU, }, |
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| 179 | { 184, CNU, CNU, CNU, }, |
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| 180 | }; |
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| 181 | |
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| 182 | static const UChar |
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| 183 | INIT_CU_AMP_POS[3][NUM_CU_AMP_CTX] = |
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| 184 | { |
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| 185 | { 154, }, |
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| 186 | { 154, }, |
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| 187 | { CNU, }, |
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| 188 | }; |
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| 189 | |
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| 190 | static const UChar |
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| 191 | INIT_PRED_MODE[3][NUM_PRED_MODE_CTX] = |
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| 192 | { |
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| 193 | { 134, }, |
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| 194 | { 149, }, |
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| 195 | { CNU, }, |
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| 196 | }; |
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| 197 | |
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| 198 | static const UChar |
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| 199 | INIT_INTRA_PRED_MODE[3][NUM_ADI_CTX] = |
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| 200 | { |
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| 201 | { 183, }, |
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| 202 | { 154, }, |
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| 203 | { 184, }, |
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| 204 | }; |
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| 205 | |
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| 206 | static const UChar |
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| 207 | INIT_CHROMA_PRED_MODE[3][NUM_CHROMA_PRED_CTX] = |
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| 208 | { |
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| 209 | { 152, 139, }, |
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| 210 | { 152, 139, }, |
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| 211 | { 63, 139, }, |
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| 212 | }; |
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| 213 | |
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| 214 | static const UChar |
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| 215 | INIT_INTER_DIR[3][NUM_INTER_DIR_CTX] = |
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| 216 | { |
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| 217 | { 95, 79, 63, 31, 31, }, |
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| 218 | { 95, 79, 63, 31, 31, }, |
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| 219 | { CNU, CNU, CNU, CNU, CNU, }, |
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| 220 | }; |
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| 221 | |
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| 222 | static const UChar |
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| 223 | INIT_MVD[3][NUM_MV_RES_CTX] = |
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| 224 | { |
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| 225 | { 169, 198, }, |
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| 226 | { 140, 198, }, |
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| 227 | { CNU, CNU, }, |
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| 228 | }; |
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| 229 | |
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| 230 | static const UChar |
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| 231 | INIT_REF_PIC[3][NUM_REF_NO_CTX] = |
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| 232 | { |
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| 233 | { 153, 153 }, |
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| 234 | { 153, 153 }, |
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| 235 | { CNU, CNU }, |
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| 236 | }; |
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| 237 | |
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| 238 | static const UChar |
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| 239 | INIT_DQP[3][NUM_DELTA_QP_CTX] = |
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| 240 | { |
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| 241 | { 154, 154, 154, }, |
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| 242 | { 154, 154, 154, }, |
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| 243 | { 154, 154, 154, }, |
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| 244 | }; |
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| 245 | |
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| 246 | static const UChar |
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| 247 | INIT_QT_CBF[3][2*NUM_QT_CBF_CTX] = |
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| 248 | { |
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| 249 | { 153, 111, CNU, CNU, CNU, 149, 92, 167, CNU, CNU, }, |
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| 250 | { 153, 111, CNU, CNU, CNU, 149, 107, 167, CNU, CNU, }, |
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| 251 | { 111, 141, CNU, CNU, CNU, 94, 138, 182, CNU, CNU, }, |
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| 252 | }; |
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| 253 | |
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| 254 | static const UChar |
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| 255 | INIT_QT_ROOT_CBF[3][NUM_QT_ROOT_CBF_CTX] = |
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| 256 | { |
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| 257 | { 79, }, |
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| 258 | { 79, }, |
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| 259 | { CNU, }, |
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| 260 | }; |
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| 261 | |
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| 262 | static const UChar |
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| 263 | INIT_LAST[3][2*NUM_CTX_LAST_FLAG_XY] = |
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| 264 | { |
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| 265 | { 125, 110, 124, 110, 95, 94, 125, 111, 111, 79, 125, 126, 111, 111, 79, |
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| 266 | 108, 123, 93, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, |
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| 267 | }, |
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| 268 | { 125, 110, 94, 110, 95, 79, 125, 111, 110, 78, 110, 111, 111, 95, 94, |
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| 269 | 108, 123, 108, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, |
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| 270 | }, |
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| 271 | { 110, 110, 124, 125, 140, 153, 125, 127, 140, 109, 111, 143, 127, 111, 79, |
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| 272 | 108, 123, 63, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, CNU, |
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| 273 | }, |
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| 274 | }; |
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| 275 | |
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| 276 | static const UChar |
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| 277 | INIT_SIG_CG_FLAG[3][2 * NUM_SIG_CG_FLAG_CTX] = |
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| 278 | { |
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| 279 | { 121, 140, |
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| 280 | 61, 154, |
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| 281 | }, |
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| 282 | { 121, 140, |
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| 283 | 61, 154, |
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| 284 | }, |
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| 285 | { 91, 171, |
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| 286 | 134, 141, |
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| 287 | }, |
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| 288 | }; |
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| 289 | |
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| 290 | static const UChar |
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| 291 | INIT_SIG_FLAG[3][NUM_SIG_FLAG_CTX] = |
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| 292 | { |
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| 293 | { 170, 154, 139, 153, 139, 123, 123, 63, 124, 166, 183, 140, 136, 153, 154, 166, 183, 140, 136, 153, 154, 166, 183, 140, 136, 153, 154, 170, 153, 138, 138, 122, 121, 122, 121, 167, 151, 183, 140, 151, 183, 140, }, |
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| 294 | { 155, 154, 139, 153, 139, 123, 123, 63, 153, 166, 183, 140, 136, 153, 154, 166, 183, 140, 136, 153, 154, 166, 183, 140, 136, 153, 154, 170, 153, 123, 123, 107, 121, 107, 121, 167, 151, 183, 140, 151, 183, 140, }, |
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| 295 | { 111, 111, 125, 110, 110, 94, 124, 108, 124, 107, 125, 141, 179, 153, 125, 107, 125, 141, 179, 153, 125, 107, 125, 141, 179, 153, 125, 140, 139, 182, 182, 152, 136, 152, 136, 153, 136, 139, 111, 136, 139, 111, }, |
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| 296 | }; |
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| 297 | |
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| 298 | static const UChar |
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| 299 | INIT_ONE_FLAG[3][NUM_ONE_FLAG_CTX] = |
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| 300 | { |
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| 301 | { 154, 196, 167, 167, 154, 152, 167, 182, 182, 134, 149, 136, 153, 121, 136, 122, 169, 208, 166, 167, 154, 152, 167, 182, }, |
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| 302 | { 154, 196, 196, 167, 154, 152, 167, 182, 182, 134, 149, 136, 153, 121, 136, 137, 169, 194, 166, 167, 154, 167, 137, 182, }, |
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| 303 | { 140, 92, 137, 138, 140, 152, 138, 139, 153, 74, 149, 92, 139, 107, 122, 152, 140, 179, 166, 182, 140, 227, 122, 197, }, |
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| 304 | }; |
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| 305 | |
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| 306 | static const UChar |
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| 307 | INIT_ABS_FLAG[3][NUM_ABS_FLAG_CTX] = |
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| 308 | { |
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| 309 | { 107, 167, 91, 107, 107, 167, }, |
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| 310 | { 107, 167, 91, 122, 107, 167, }, |
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| 311 | { 138, 153, 136, 167, 152, 152, }, |
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| 312 | }; |
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| 313 | |
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| 314 | static const UChar |
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| 315 | INIT_MVP_IDX[3][NUM_MVP_IDX_CTX] = |
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| 316 | { |
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| 317 | { 168, CNU, }, |
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| 318 | { 168, CNU, }, |
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| 319 | { CNU, CNU, }, |
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| 320 | }; |
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| 321 | |
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| 322 | static const UChar |
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| 323 | INIT_SAO_MERGE_FLAG[3][NUM_SAO_MERGE_FLAG_CTX] = |
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| 324 | { |
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| 325 | { 153, }, |
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| 326 | { 153, }, |
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| 327 | { 153, }, |
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| 328 | }; |
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| 329 | |
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| 330 | static const UChar |
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| 331 | INIT_SAO_TYPE_IDX[3][NUM_SAO_TYPE_IDX_CTX] = |
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| 332 | { |
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| 333 | #if FIX827 |
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| 334 | { 160, }, |
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| 335 | { 185, }, |
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| 336 | { 200, }, |
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| 337 | #else |
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| 338 | { 200, }, |
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| 339 | { 185, }, |
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| 340 | { 160, }, |
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| 341 | #endif |
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| 342 | }; |
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| 343 | |
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| 344 | static const UChar |
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| 345 | INIT_TRANS_SUBDIV_FLAG[3][NUM_TRANS_SUBDIV_FLAG_CTX] = |
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| 346 | { |
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| 347 | #if FIX712 |
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| 348 | { 224, 167, 122, }, |
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| 349 | { 124, 138, 94, }, |
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| 350 | { 153, 138, 138, }, |
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| 351 | #else |
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| 352 | { 153, 138, 138, }, |
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| 353 | { 124, 138, 94, }, |
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| 354 | { 224, 167, 122, }, |
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| 355 | #endif |
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| 356 | }; |
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| 357 | |
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| 358 | static const UChar |
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| 359 | INIT_TRANSFORMSKIP_FLAG[3][2*NUM_TRANSFORMSKIP_FLAG_CTX] = |
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| 360 | { |
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| 361 | { 139, 139}, |
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| 362 | { 139, 139}, |
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| 363 | { 139, 139}, |
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| 364 | }; |
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[504] | 365 | |
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| 366 | #if H_3D_ARP |
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| 367 | static const UChar |
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| 368 | INIT_ARPW[3][NUM_ARPW_CTX] = |
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| 369 | { |
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| 370 | { 154, 154, 154, 154 }, |
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| 371 | { 154, 154, 154, 154 }, |
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| 372 | { 154, 154, 154, 154 }, |
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| 373 | }; |
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| 374 | #endif |
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| 375 | |
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| 376 | #if H_3D_IC |
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| 377 | static const UChar |
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| 378 | INIT_IC_FLAG[3][NUM_IC_FLAG_CTX] = |
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| 379 | { |
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| 380 | { CNU, CNU, CNU, }, |
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| 381 | { 197, 185, 201, }, |
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| 382 | { 197, 185, 201, }, |
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| 383 | }; |
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| 384 | #endif |
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[531] | 385 | #if H_3D_DIM |
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[561] | 386 | #if ZJU_DEPTH_INTRA_MODE_E0204 |
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| 387 | static const UChar |
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| 388 | INIT_DEPTH_INTRA_MODE[3][NUM_DEPTH_INTRA_MODE_CTX] = |
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| 389 | { |
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| 390 | {0, 0, 64, 168, 168, 124, CNU, 0}, |
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| 391 | {0, 64, 0, 183, CNU, 108, 0, 0}, |
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| 392 | {64, 0, CNU, CNU, 168, 109, 0, 0} |
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| 393 | }; |
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| 394 | #else |
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[531] | 395 | static const UChar |
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| 396 | INIT_DEPTH_INTRA_MODE[3][NUM_DEPTH_INTRA_MODE_CTX] = |
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| 397 | { |
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| 398 | {0, 0, 64, 0, CNU, 0, CNU, 0}, |
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| 399 | {0, 64, 0, CNU, 0, CNU, 0, 0}, |
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| 400 | {64, 0, CNU, 0, CNU, 0, 0, 0} |
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| 401 | }; |
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[561] | 402 | #endif |
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[531] | 403 | static const UChar |
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| 404 | INIT_DDC_FLAG[3][NUM_DDC_FLAG_CTX] = |
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| 405 | { |
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| 406 | {0 , CNU}, |
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| 407 | {0 , CNU}, |
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| 408 | {64, CNU} |
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| 409 | }; |
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| 410 | static const UChar |
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| 411 | INIT_DDC_DATA[3][NUM_DDC_DATA_CTX] = |
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| 412 | { |
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| 413 | { CNU, CNU }, |
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| 414 | { CNU, CNU }, |
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| 415 | { CNU, CNU }, |
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| 416 | }; |
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| 417 | #if H_3D_DIM_DMM |
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| 418 | static const UChar |
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| 419 | INIT_DMM1_DATA[3][NUM_DMM1_DATA_CTX] = |
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| 420 | { |
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| 421 | { CNU }, |
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| 422 | { CNU }, |
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| 423 | { CNU }, |
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| 424 | }; |
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[554] | 425 | #if !SEC_DMM2_E0146 |
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[531] | 426 | static const UChar |
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| 427 | INIT_DMM2_DATA[3][NUM_DMM2_DATA_CTX] = |
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| 428 | { |
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| 429 | { CNU }, |
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| 430 | { CNU }, |
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| 431 | { CNU }, |
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| 432 | }; |
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[554] | 433 | #endif |
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[531] | 434 | static const UChar |
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| 435 | INIT_DMM3_DATA[3][NUM_DMM3_DATA_CTX] = |
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| 436 | { |
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| 437 | { CNU }, |
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| 438 | { CNU }, |
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| 439 | { CNU }, |
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| 440 | }; |
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| 441 | #endif |
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| 442 | #if H_3D_DIM_RBC |
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| 443 | static const UChar |
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| 444 | INIT_RBC_DATA[3][NUM_RBC_DATA_CTX] = |
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| 445 | { |
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| 446 | { CNU }, |
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| 447 | { CNU }, |
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| 448 | { CNU }, |
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| 449 | }; |
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| 450 | #endif |
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| 451 | #if H_3D_DIM_SDC |
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| 452 | static const UChar |
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| 453 | INIT_SDC_RESIDUAL_FLAG[3][SDC_NUM_RESIDUAL_FLAG_CTX] = |
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| 454 | { |
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| 455 | { CNU }, |
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| 456 | { CNU }, |
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| 457 | { CNU }, |
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| 458 | }; |
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| 459 | static const UChar |
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| 460 | INIT_SDC_RESIDUAL[3][SDC_NUM_RESIDUAL_CTX] = |
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| 461 | { |
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| 462 | { 155 }, |
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| 463 | { 155 }, |
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| 464 | { 155 }, |
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| 465 | }; |
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| 466 | #endif |
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| 467 | #endif |
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[504] | 468 | |
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[324] | 469 | //! \} |
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| 470 | |
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| 471 | |
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| 472 | #endif |
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